Xputers: FAQ (2)
Xputers: FAQ (1)
Several sequencers in one machine?
What is a Map-oriented Machine (MoM)?
What is the Kress Machine?
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If you are not familiar with Xputers, first see special page explaining all about data sequencers. In a von Neumann machine you may have only one sequencer. But the Xputer paradigm permits to have several sequencers in a single machine . This, for example makes sense not only in a number of DSP algorithms, such as FFT (Fast Fourier Transforms), like the constant gemometry FFT. Fig. 5 illustrates the use of three data seuqencers for a 16 point constant gemometry FFT. The 2-by-2 scan window no. 1, sequenced by sequencer no. 1, communicates throug the data path with scan windows no. 2 and 3. A scan window is a kind of smart register file. Fig. 24 illustrates, how the 3 scan windows are sequenced throutgh memory space.
The MoM (Map-oriented Machine) is an Xputer architecture based on 2-dimensional memory organization. A MoM features 2-dimensional scan windows, size adjustable at run time. A scan window buffers a 2-dimensional memory subspace, such as 2 by 3 words, for example (see section 3 of FAQ on Xputers). The scan window is implemented by a smart processor-to-memory interface (see figure 6), which is a smart register file featuring various aids to save memory access cycles . 2D memory space supports excellent visualization of computations and data dependencies .
[rDPA: see Kress Array | how SMIF accelerates]
With progress of technology the processor / memory communication gap widens more and more. Even very large caches cannot bridge this gap completely. Caches accelerate only software with highly iterative loops on write once (into cache) and read very often (from cache). Cache efficiency is probabilistic, and is very low for a number of important algorithms. For Xputers, however, caches do not help at all, since Xputers' compilers convert loops into hardware configurations. In this context the smart memory interface (see fig. 6) uses deterministic methods to reduce the number of memory cycles - compared to a von Neumann implementation of the same algorithm .
< >Fig. 7. Xputer Architectures - The Kress Machine:
[All about Data Sequencers | rDPA: see Kress Array]
< >Fig. 8. Basic Structure of the Kress Machine:
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