Program

 

Regular papers presentations: 20 mins + 5 mins Q&A

Short papers presentations: 10 mins + 5 mins Q&A

 

Wednesday

08.30 – 09.00

 

Opening Remarks

 

 

09.00 – 10.00

 

Keynote

Hong Jiang: An Application-Aware Approach to Systems Support for Big Data

 

10.00 – 10.30

 

Break

 

 

10.30 – 12.30

 

Compilers and Design Tools

 

Regular papers

 

Symbolic Parallelization of Loop Programs for Massively Parallel Processor Arrays
Jürgen Teich, Alexandru Tanase and Frank Hannig

 

Loop Program Mapping and Compact Code Generation for Programmable Hardware Accelerators
Srinivas Boppu, Frank Hannig and Jürgen Teich

 

Aspect Driven Compilation for Dataflow Designs
Paul Grigoras, Xinyu Niu, Jose G. F. Coutinho, Wayne Luk, Jacob Bower and Oliver Pell

 

Short papers

 

Enabling Development of OpenCL Applications on FPGA platforms
Kavya Shagrithaya, Krzysztof Kepa and Peter Athanas

 

Modelling Communication Overhead for Accessing Local Memories in Hardware Accelerators
Alok Prakash, Christopher T. Clarke, Siew-Kei Lam and Thambipillai Srikanthan

 

Cache Partitioning and Scheduling for Energy Optimization of Real-Time MPSoCs
Gang Chen, Kai Huang, Jia Huang and Alois Knoll

 

12.30 – 13.30

 

 

Lunch Break

 

 

13.30 – 15.10

 

Application Acceleration 1

 

Regular papers

 

Accelerating HAC Estimation for Multivariate Time Series
Ce Guo and Wayne Luk

 

Toward a Fast Stochastic Simulation Processor for Biochemical Reaction Networks
Hyungman Park and Andreas Gerstlauer

 

A High-Speed and Large-Scale Dictionary Matching Engine for Information Extraction Systems
Kanak Agarwal and Raphael Polig

 

Efficient Implementation of Cryptographic Primitives on the GA144 Multi-core Architecture
Tobias Schneider, Ingo von Maurich and Tim Güneysu

 

 

15.15 – 16.00

 

 

Poster Session I Break

 

Posters

 

iVAMS: Intelligent Metamodel-Integrated Verilog-AMS for Circuit-Accurate System-Level Mixed-Signal Design Exploration
Geng Zheng, Saraju Mohanty, Elias Kougianos and Oghenekarho Okobiah

 

Design Space Exploration for Reliable mm-Wave Wireless NoC Architectures
Paul Wettin, Partha Pande, Deukhyoun Heo, Benjamin Belzer, Amlan Ganguly and Sujay Deb

 

Migration-aware Loop Retiming for STT-RAM based Hybrid Cache for Embedded Systems
Keni Qiu, Mengying Zhao, Chenchen Fu, Liang Shi and Chun Jason Xue

 

An Exploration of the Design Space for Application-Specific ARM Processors for Web Browsing
Gabriel Yessin, Lubomir Riha, David Mayhew and Tarek El-Ghazawi

 

Virtual Finite-State-Machine Architectures for Fast Compilation and Portability
Lu Hao and Greg Stitt

 

Selective Validations for Efficient Protections on Coarse-Grained Reconfigurable Architectures
Jihoon Kang, Yohan Ko, Jongwon Lee, Yongjoo Kim, Hwisoo So, Kyoungwoo Lee and Yunheung Paek

 

Pseudo-Constant Logic Optimization
Aaron Landy and Greg Stitt

 

Fast Lossless Image Compression with Radiation Hardening By Hardware/Software Co- Design on Platform FPGAs
Andrew Schmidt and Matthew French

 

OCP: Offload Co-Processor for Energy Efficiency in Embedded Mobile Systems
Jie Tang, Chen Liu, Yu-Liang Chou and Shaoshan Liu

 

Standard Deviation of CPI: A New Metric to Evaluate Architectural Time Predictability
Wei Zhang and Yiqiang Ding

 

Synthesizing Accurate Formulas for the Floating-Point Arithmetic
Arnault Ioualalen and Matthieu Martel

 

 

16.00 – 18.00

 

Computer Arithmetic 

 

Regular papers

 

The Denormal Logarithmic Number System
Mark G. Arnold and Sylvain Collange

 

A Compact and Scalable RNS Architecture
Pedro Miguens Matutino, Ricardo Chaves and Leonel Sousa

 

3D Stacked Wide-Operand Adders: A Case Study
George R. Voicu, Mihai Lefter, Marius Enachescu and Sorin Cotofana

 

Short papers

 

An Effective New CRT Based Reverse Converter for a Novel Moduli Set {2^{2n+1}-1, 2^{2n+1}, 2^{2n}-1}
Edem Kwedzo Bankas, Kazeem Alagbe Gbolagade and Sorin Dan Cotofana

 

Fused Floating-Point Two-term Sum-of-Squares Unit
Jae Hong Min and Earl Swartzlander

 

FARHAD: a Fault-Tolerant Power-Aware Hybrid Adder for Add Intensive Applications
Mohammad Hossein Hajkazemi, Amirali Baniasadi and Hossein Asadi

 

 

Thursday

 

08.30 – 09.00

 

Announcements, Best Paper Awards

 

 

09.00 – 10.00

 

Keynote

Josep Torrellas: Extreme Scale Computer Architecture: Energy Efficiency from the Ground Up

 

 

10.00 – 10.30

 

Break

 

 

10.30 – 12.30

  

Linear Algebra and Signal Processing

 

Regular papers

 

A Practical Measure of FPGA Floating Point Acceleration of High Performance Computing
John Cappello and Dave Strenski

 

Sparse Matrix-Vector Multiply on the Texas Instruments C6678 DSP
Yang Gao and Jason Bakos

 

Transforming A Linear Algebra Core to An FFT Accelerator
Ardavan Pedram, John McCalpin and Andreas Gerstlauer

 

Short papers

 

Reduce, Reuse, Recycle (R3): a Design Methodology for Sparse Matrix Vector Multiplication on Reconfigurable Platforms
Kevin Townsend and Joseph Zambreno

 

Power Optimization of Sum-of-Products Design for Signal Processing Applications
Seok Won Heo, Suk Joong Huh and Miloš Ercegovac

 

An Efficient & Reconfigurable FPGA and ASIC Implementation of a Spectral Doppler Ultrasound Imaging System
Adam Page and Tinoosh Mohsenin

 

 

12.30 – 13.30

 

Lunch Break

 

 

13.30 – 15.10

 

Virtualization and Portability

 

Regular papers

 

Hardware Acceleration for Just-In-Time Compilation on Heterogeneous Embedded Systems
Alexandre Carbon, Yves Lhuillier and Henri-Pierre Charles

 

Reconfigurable Computing Middleware for Application Portability and Productivity
Robert Kirchgessner, Alan George and Herman Lam

 

Microkernel Hypervisor for a Hybrid ARM-FPGA Platform
Khoa D. Pham, Abhishek K. Jain, Jin Cui, Suhaib A. Fahmy and Douglas L. Maskell

 

Private configuration environments (PCE) for efficient reconfiguration, in CGRAs
Muhammad Adeel Tajammul, Syed Mohammad Asad Hassan Jafri, Ahmed Hemani, Juha Plosila and Hannu Tenhunen

 

 

15.15 – 16.00

 

Poster Session II Break

 

Posters

 

A Comparison of Correntropy-Based Feature Tracking on FPGAs and GPUs
Patrick Cooke, Jeremy Fowers, Lee Hunt and Greg Stitt

 

BioBlaze: Multi-Core SIMD ASIP for DNA Sequence Alignment
Nuno Neves, Nuno Sebastião, André Patrício, David Matos, Pedro Tomás, Paulo Flores and Nuno Roma

 

A Real-Time Implementation of the Total Focusing Method for Rapid and Precise Diagnostic in Non Destruction Evaluation
Mickael Njiki, Abdelhafid Elouardi, Samir Bouaziz, Olivier Casula and Olivier Roy

 

Novel Multi-Layer Network Decomposition Boosting Acceleration of Multi-core Algorithms
Athanasios K. Grivas, Terrence Mak, Alex Yakovlev and Jonny Wray

 

On The Performance of Code Block Segmentation for LTE-Advanced
Karlo Lenzi, Felipe Augusto Pereira de Figueiredo, José Arnaldo Bianco F. and Fabricio L. Figueiredo

 

Accelerating the Performance of Stochastic Encoding-based Computations by Sharing Bits in Consecutive Bit Streams
Peng Li and David Lilja

 

FPGA-Based HPC Application Design for Non-Experts
David Uliana, Krzysztof Kepa and Peter Athanas

 

Accelerating Nonlinear Diffusion Tensor Estimation for Medical Image Processing Using High Performance GPU Clusters
Vinh Q. Dang, Esam El-Araby, Lam H. Dao and Lin-Ching Chang

 

FPGA and ASIC Square Root Designs for High Performance and Power Efficiency
Shashank Suresh, Spiridon Beldianu and Sotirios Ziavras

 

Linear Algebra Computations in Heterogeneous Systems
Sam Skalicky, Sonia Lopez Alarcon and Marcin Lukowiak

 

Unifying CORDIC and Box-Muller Algorithms: An Accurate and Efficient Gaussian Random Number Generator
Jamshaid Sarwar Malik, Ahmed Hemani and N.D Gohar

 

 

16.00 – 18.00

 

Adaptive Architectures

 

Regular papers

 

A highly efficient, thread-safe software cache implementation for tightly-coupled multicore clusters
Christian Pinto and Luca Benini

 

Incorporating Temperature-Leakage Interdependency into Dynamic Voltage Scaling for Real-Time Systems
Junjun Gu and Gang Qu

 

Hybrid SPM-Cache Architectures to Achieve High Time Predictability and Performance
Wei Zhang and Yiqiang Ding

 

Short papers

 

A Low-Power Content-Addressable-Memory Based on Clustered-Sparse-Networks
Hooman Jarollahi, Vincent Gripon, Naoya Onizawa and Warren J. Gross

 

Exploring hardware support for scaling irregular applications on multi-node multi-core architectures
Simone Secchi, Marco Ceriani, Antonino Tumeo, Oreste Villa, Luigi Raffo and Gianluca Palermo

 

Design-for-Adaptivity of Microarchitectures
Maxim Rykunov, Andrey Mokhov, Danil Sokolov, Alex Yakovlev and Albert Koelmans

 

Friday

 

08.30 – 10.30

 

Keynote

 

Sun-Yuan Kung: From Green Computing to Big-Data Learning: A Kernel Learning Perspective

 

 

Featured Invited Talks

 

Roozbeh Jafari: Wireless Health: Challenges and Opportunities

 

Reiner Hartenstein: The Tunnel Vision Syndrome: Massively Delaying Progress

 

10.30 – 11.00

 

Break

 

 

11.00 – 13.30

 

Application Acceleration 2

 

Regular papers

 

GPU Acceleration of Data Assembly in Finite Element Methods and Its Energy Implications
Li Tang, Xiaobo Sharon Hu, Danny Ziyi Chen, Michael T. Niemier, Richard F. Barrett, Simon D. Hammond and Ming-Yu Hsieh

 

A Distributed CPU-GPU Framework for Pairwise Alignments on Large-Scale Sequence Datasets
Da Li, Kittisak Sajjapongse, Huan Truong, Gavin Conant and Michela Becchi

 

A Reconfigurable Application-specific Instruction-set Processor for Fast Fourier Transform Processing
Waqar Hussain, Xiaolin Chen, Gerd Ascheid and Jari Nurmi

 

Correctly Rounded Architectures for Floating-Point Multi-Operand Addition and Dot-Product Computation
Yao Tao, Gao Deyuan, Fan Xiaoya and Jari Nurmi

 

Short papers

 

Highly Scalable On-the-Fly Interleaved Address Generation for UMTS/HSPA+ Parallel Turbo Decoder
Aida Vosoughi, Guohui Wang, Hao Shen, Joseph R. Cavallaro and Yuanbin Guo

 

Implementing High-Performance, Low-Power FPGA-based Optical Flow Accelerators in C
Joshua Monson, Michael Wirthlin and Brad Hutchings

 

A Scalable RC Architecture for Accelerating Mean-Shift Clustering
Stefan Craciun, Gongyu Wang, Alan George, Herman Lam and Jose Principe

 

 

 

 

Additional information