Achievements of

Prof. Reiner Hartenstein and his team*

(last incomplete update in 2016)


[ keynotes | Hartenstein's page | biography | short bio | awards | Xputers | KARL | E.I.S. history | more achievements | homepage ]


Work done and awards received:

Keynotes and other invited presentations:

Refereed papers / presentations:



List of Achievements





The first book (1977) on a HDL introducing a methodology for Structured VLSI Design - a bestseller (5000 sold):
  1. R. Hartenstein:  "Fundamentals of Structured Hardware Design - A Design Language Approach at Register Level"; North Holland Publ. Co./American Elsevier (Elsevier Scientific), Amsterdam / New York, 1977

Earlier KARL-related publications:

  1. R. Hartenstein: Towards a Language for the Description of IC Chips; SIGMICRO Newsletter .vol. 4, no. 4, 1973
  2. R. Hartenstein: A Halfbaked Idea on a set of Register Transfer Primitives; SIGMICRO Newsletter vol. 4,  no. 3, 1973



The first regularly scheduled Mead & Conway style university course "on the continent" (Europe and Asia):   (summer semester 1980 at CS department, University of  Kaiserslautern)

--- the first
in the world except USA (starting end of 1978) and UK (starting winter semester 1979/80) -- later version:

  1. R. Hartenstein: (Standort Deutschland: Wozu noch Mikrochips?) - Einführung in die Methoden der Technischen Informatik; ITpress Verlag Bruchsal / Chicago, 1994



Authoring and implementing KARL-II,  throughout the 80ies the most successful HDL* (1st rank before Ella). see List of licensee sites - List of 2nd party tools interfaced to it - quotation index  - KARL-related literature  Implementation and application of KARL has been supported as the CVT project and the CVS projects (grants: a total of about 85 million ECU from 1983 - 1990) by the European Union within the framework of the ESPRIT programme. (In the 90ies VHDL and Verilog took over.)
  1. R. Hartenstein: KARL and ABL; in J. Mermet (editor): Fundamentals and Standards in Hardware Description Languages; Kluwer Academic Publishers, 1993



KARL-II the first implemented HDL including "wiring operator" primitives  (shuffle, butterfly and many others) - useful for module generator generators, structured VLSI design, later also used by Vasily Moshnyaga and Hiroto Yasuura, University of Kyoto, for a module generator:
  1. V. Moshnyaga, H. Yasuura et al.: A Data-Path Modules Design from Algorithmic Representations;  Pro. WG10.5 IFIP Workshop on Synthesis, Generation and Portability of Library Blocks for ASIC Design, March 1992.
  2. V. Moshnyaga, H. Yasuura et al.: A Language for Designing Module Generators; Proc. Synthesis and Simulation Meeting and International Interchange (SASIMI'92), pp.383-392,  April 1992.



the first implemented RT level HDL including fully fledged chip planning primitives*  (layer expression, slice expressions, and abutment expressions with port matching syntax).
  1. R. Hartenstein: The use of KARL for the description of Integrated Circuits; iin: R. Piloty (editor):  Proc. Intl. Workshop on Computer Hardware Description Languages, Darmstadt, 1974, ACM Lecture Notes, German Chapter ACM 1975
  2. R. Hartenstein: Wiring Algebra for Specification of VLSI Design Problems; SIGDA Newsletter, Aug. 1980
  3. R. Hartenstein: KARL and ABL; in J. Mermet (editor): Fundamentals and Standards in Hardware Description Languages; Kluwer Academic Publishers, 1993
  4. G. Girardi, R. Hartenstein: ABL-Specification -Draft-; CVT-report, Torino, Italy / Kaiserslautern, 1983
  5. G. Girardi, R. Hartenstein, U. Welters: ABLED: a RT level Schematic Editor and Simulator user Interface; Int`l EUROMICRO Symposium, Brussels, 1985, North Holland Publishing Co, Amsterdam 1985

*) at at that time  µFP (Mary Sheeran, Ph. D. thesis, submitted Nov. 1983) was the only other HDL including a topological operator to express relative position of operators (but port specs have not not included)



Authoring and Implementation of KARL-III (also called CVS_BK or CVS Behavioral KARL), a KARL-II extension also supporting the inclusion of procedural descriptions.
  1. KARL-III Primer (draft), CVT report, Univ. Kaiserslautern, April 1985
  2. A.Bonomo, G.Girardi, R. Hartenstein, L.Lavagno, R. Hauck: Syntax Diagrams of the CVS_BK Language (CVS Behavioral KARL); ESPRIT / CVS report, CSELT, Torino, Italy / Univ. Kaiserslautern, Germany, Febr. 1987
  3. A.Bonomo, G.Girardi, R. Hartenstein, L.Lavagno, R.Hauck: Semantic Specification of CVS_BK Language (CVS Behavioral KARL); ESPRIT / CVS report, CSELT, Torino, Italy / Univ. Kaiserslautern, Germany, Febr. 1987


The first graphical HDL editor implemented, also  including floor planning features.  The only earlier graphical HDL having been implemented at University of Missouri at Rolla was merely a HDL-oriented schematics entry system.
  1. R. Hartenstein: The use of the block diagram language ABL; in: R. Piloty (editor): Proceedings of the Intl. Workshop on Computer Hardware Description Languages, Darmstadt, 1974, ACM Lecture  Notes, German Chapter of the ACM 1975
  2. G. Girardi, U. Welters et al.: ABLED: a RT level Schematic Editor and Simulator user Interface; Int`l EUROMICRO Symposium, Brussels, 1985, North Holland Publishing Co, Amsterdam 1985
  3. A. Bonomo, G. Girardi, A. Leece, L. Magiulli: GENMON: a specialized ABL editor for design methodology descriptions; 2nd ABL and KARL User group workshop (ABAKUS workshop), Igls, Austria, 1988


Shifting Functional Design Verification Toward RT Level
  1. W. Nebel et al.: Shifting Functional Design Verification Toward RT Level by Automatic Register Transfer Net Extraction; IFIP CHDL'87, Amsterdam, 1987
  2. W. Nebel et al.: Functional Design Verification by Register Transfer Net Extraction from Integrated Circuit Layout Data; IEEE COMPEURO, Hamburg, 1987
  3. W. Nebel: -REX- Automatic Extraction of RT-Level Descriptions from Integrated Circuit Layout Data;  Ph. D. Dissertation, University of Kaiserslautern, 1986 -



The first proposed term rewriting (TR) approach for structured VLSI synthesis.
All earlier TR approaches in EDA deserved verification (bottom-up approach), whereas the one proposed by Kaiserslautern is the first one which deserves synthesis (top-down approach). Also see here
    1. R. Hartenstein: Wiring Algebra for Specification of VLSI Design Problems; SIGDA Newsletter, Aug. 1980



Invented and implemented the data-stream-based  anti machine paradigm (also sometimes called Xputer machine paradigm (XMP))  using data counters instead of a program counter: the counterpart of the instruction-stream-based "von Neumann" machine. There are more than 200 Xputer-related publications.

This is the first general machine paradigm for processors or arrays using soft data paths.
Its data counters are co-located with (auto-sequencing) data memory banks (not co-located with the data path)

Data-stream-based computing also coming along with the anti machine paradigm and related compilation methods have recently been recognized as a general method to cope with the memory wall, having been the main reason of stalled progress in high performance computing during the past 2 decades.
  1. R. Hartenstein (invited presentation): MoM - A Semi-von-Neumann Accelerator Architecture; Centro Technologica para Informatica, Campinas, Brasil, 1987
  2. R. Hartenstein, A. Hirschbiel, M. Weber: MOM - Map Oriented Machine, Proc. Int'l Workshop on Hardware Accelerators, Oxford, UK, Oct. 1987;
  3. R. Hartenstein, A. Hirschbiel, M. Weber: MOM - Map Oriented Machine, International Conference on Parallel Processing and Applications, L'Aquila, Italy, Sept. 1987.
  4. R. Hartenstein,  A.G. Hirschbiel, M.Weber: MOM - a partly custom-designed architecture compared to standard hardware, Proc. IEEE COMPEURO, Hamburg 1989, IEEE Press, 1989
  5. R. Hartenstein, A.G. Hirschbiel, M.Weber: A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware; InfoJapan'90- International Conference memorating the 30th Anniversary of the Computer Society of Japan, Tokyo, Japan, 1990
  6. (see above) Invited reprint in Future Generation Computer Systems 7, 1991 / 1992, p. 181-198, North Holland
  7. R. Hartenstein,  A.G. Hirschbiel, M. Riedmüller, K. Schmidt, M.Weber: A Novel ASIC Design Method based on a Machine Paradigm; IEEE-JSSC - Journal of Solid State Circuits , Vol. 26, No. 7, pp. 975-989, July 1991



invented and implemented Auto-sequencing Data Memory principles using a novel address generator methodology (GAG: generic address generators) needed for anti machine architectures.

The anti machine based on
Auto-sequencing Data Memory has recently been recognized as a general method to cope with the memory wall, the main reason of stalled progress in supercomputing during the past 2 decades.
  1. R. Hartenstein,  A. Hirschbiel, M. Riedmüller, K. Schmidt, M.Weber (second best paper award): A Novel high-performance Machine Paradigm Using Auto-sequencing Data Memory; 1991 Hawaii International Conference on Systems Sciences, Koloa, Kauai, Hawaii, 1991
  2. R. Hartenstein, M. Herz, M. Miranda, E. Brockmeyer, F. Catthoor (invited paper): Memory Organisation for Stream-based Reconfigurable Computing; 9th IEEE International Conference on Electronics, Circuits and Systems - ICECS 2002,  September 15-18, 2002, Dubrovnik, Croatia - pdf - pps-ppt
  3. The KressArray Page



The first data context transforms to optimize storage schemes for anti machines by scan pattern transforms (e. g. rotation, shearing and others) - avoiding address computation overhead  as well as avoiding or reducing instruction fetch at run time  ...

  1. A. Hirschbiel: A Novel Processor Architecture Based on Auto Data Sequencing and Low Level Parallelism, Ph. D. Dissertation 1991
  2. M. Herz: High Performance Memory Communication Architectures for Coarse-grained Reconfigurable Computing Systems; Dissertation 2001, Kaiserslautern University of Technology -  pdf
  3. R. Hartenstein, M. Herz, M. Miranda, E. Brockmeyer, F. Catthoor (invited paper): Memory Organisation for Stream-based Reconfigurable Computing; 9th IEEE International Conference on Electronics, Circuits and Systems - ICECS 2002,  September 15-18, 2002, Dubrovnik, Croatia - pdf - pps-ppt


The first general purpose high level programming language for anti machines (MoPL): data-stream-based (data counter usage) - instead of instruction-stream-based as known from von Neumann.

  1. A. Ast, J. Becker, et al.: Data-procedural Languages for FPL-based Machines; 4th Int. Workshop On Field Programmable Logic And Applications, FPL'94, Prague, September 7-10, 1994, Lecture Notes in Computer Science, Springer, 1994.
  2. A. Ast, J. Becker, et al.: Data-procedural Languages for FPL-based Machines; Universität Kaiserslautern, Fachbereich Informatik, Interner Bericht, Nr. 264/95, 1995


The first automatically partitioning compiler for software/configware co-design
  1. J. Becker: A Partitioning Compiler for Computers with Xputer-based Accelerators, Ph. D. Dissertation 1997, Kaiserslautern University of Technology  - URL - pdf
  2. K. Schmidt: A Program Partitioning, Restructuring, and Mapping Method for Xputers, Ph. D. Dissertation 1994, Kaiserslautern University of Technology  - available from publisher Shaker Verlag, ISBN: 3-8265-0495-X
  3.  J. Becker, et al.: A Profiling-Driven Hardware/Software Partitioning of High Level Language Specification; IFIP International Workshop on Logic and Architecture Synthesis, Grenoble, France, 18. - 19. Dezember 1995



The first generalization of the systolic array  (KressArray) implemented along with synthesis tool (DPSS). Originally systolic arrays could be used only for algorithms with strictly regular data dependencies, because their synthesis metholds yielded only arrays with uniform processing elements, and with only linear pipes. Kaiserslauterns new DPSS synthesis method, however,  supports all applications also with extremely irregular data dependencies, so that also the use of reconfigurable platforms makes sense. This generalization has been obtained by using simulated annealing instead of linear projection or algebraic methods for synthesis.
  1. R. Kress: A Fast Reconfigurable ALU for Xputers, Ph. D. Dissertation 1996, Kaiserslautern University of Technology  - please, request printed version
  2. R. Kress et al.: A Data path Synthesis System for the Reconfigurable Data path Architecture; Asia and South Pacific Design Automation Conference, ASP-DAC'95, Nippon Convention Center, Makuhari, Chiba, Japan, Aug./Sept. 1995



The first design space explorer implemented for coarse grain reconfigurable arrays, supporting a wide variety of array architectures and PE architectures - also including architectures requiring extremely rich interconnect resources.
  1. U. Nageldinger: Coarse-grained Reconfigurable Architectures Design Space Exploration; Ph. D. Dissertation, 2001 -  pdf
  2. U. Nageldinger et al.: Design-Space Exploration of Low Power Coarse Grained Reconfigurable Data path Array Architectures;  Proc. PATMOS 2000,  International Workshop - Power and Timing Modeling, Optimization and Simulation, Göttingen, Germany - September 13-15, 2000


Reiner Hartenstein predicted the decline of Germany's role as a High Tech Innovator - already in 1994 and even much earlier.

  1. R. Hartenstein: Null Bock auf High Tech; ITpress Verlag, 1994 -- intensions of this book
  2. R. Hartenstein: Articles in nationwide newspapers.
Also see here.


Lobbying efforts in curriculum development.

Hartenstein has been interested in Computer architecture education already in the 70ies.
  1. R. Hartenstein: Increased Hardware Complexity  -  A Challenge to Computer Science Education; 1st Int'l. Symposium for Computer Architecture (ISCA), Gainesville, Florida, Dec. 9. - 11, 1973
More recently Reiner Hartenstein lobbies for upgrading CS-related curricula to keep future graduates competitive in the job market in a world of off-shoring and of the rapidly growing dominance of embedded systems development, also heavily using reconfigurable platforms. Instead of the de facto dominance (the almost-monopoly) of an instruction-stream-based (von Neumann) mind set he advocates the early introduction, already for freshmen, of a duality of machine paradigms: instruction-stream-based and data-stream-based (von Neuann and anti machine), such that all graduates of CS-related university programs should be qualified to cope with hardware / configware / software partitioning decisions.

It is Hartenstein's achievement, that he receives an increasing number of invitations to give talks on this complex of topic areas.(see erecent talks).
  1. R. Hartenstein (keynote): Reconfigurable HPC: torpedoed by Deficits in Education ? ; Workshop on Reconfigurable Systems for HPC (RHPC); July 21, 2004, to be held in conjunction with HPC Asia 2004, 7th International Conference on High Performance Computing and Grid in Asia Pacific Region,  July 20 - 22, 2004, Omiya Sonic City, Tokyo Area, Japan   (ppt)  (pdf)
  2. R. Hartenstein (keynote):  The Changing Role of Computer Architecture Education within CS Curricula;  Workshop on Computer Architecture Education (WCAE 2004) June 19, 2004, at 31st International Symposium on Computer Architecture (ISCA),  Munich, Germany, June 19-23, 2004   (ppt)  (pdf)

more keynotes



*) CSG = Computer Structures Group (Rechnerstrukturen) at University of Kaiserslautern
 
 



(last incomplete update in 2016)

 © Copyright 2001, University of Kaiserslautern, Kaiserslautern, Germany Webmaster